SMIC and CXMT Face Soaring Costs as They Push DUV Lithography to Its Limits

One-third. That is the estimated output gap between Chinese memory maker CXMT and its Western rivals, according to a June report from Morgan Stanley. The bank found that CXMT produces only about one-third as many bits per wafer as competitors who have access to extreme ultraviolet lithography. This stark figure highlights the financial and technical burden facing Chinese manufacturers as they attempt to close the gap in advanced semiconductor production without the industry’s most powerful equipment.

Export controls have successfully blocked ASML’s EUV machines from entering China, forcing local chipmakers to rely on older deep ultraviolet DUV tools. While these machines use 193nm light, they can still produce capable silicon through a technique called multiple patterning. This method involves splitting a complex chip design into several simpler patterns and exposing the wafer multiple times. Experts note that while this approach allows for the creation of 7nm and even near 5nm class processors, it introduces significant trade-offs that impact cost, quality, and speed.

The economic penalty for this workaround is substantial. Chris Mack, co-founder and CTO of Fractilia, explained that industry wisdom suggests three exposures on a 193 immersion tool cost about the same as one EUV pass. However, the balance shifts sharply at four masks, where EUV becomes the cheaper option. Since Chinese firms often require more than four exposures to achieve finer densities, their bills climb with every additional step. This inefficiency is compounded by physical limitations, as each new pattern must align perfectly with previous ones. More exposures lead to accumulated overlay errors, forcing designers to add extra space around features. This enlarges the chip size and reduces the number of usable dies per wafer, a costly mistake when wafers cost tens of thousands of dollars.

Despite these hurdles, Chinese progress has been notable. A 2023 teardown of the Huawei Mate 60 Pro revealed that SMIC’s Kirin 9000S processor was built using a second-generation 7nm-class process without EUV. Recent analysis suggests SMIC has moved its DUV-based process closer to 5nm density, though it still trails the leading nodes from TSMC and Samsung. In the memory sector, CXMT is currently producing 1-alpha DRAM without EUV. Morgan Stanley estimates that CXMT will maintain this technology while expanding capacity, potentially raising its share of global DRAM bit supply from 14% in 2026 to 16% by 2028.

The path forward for Chinese manufacturers involves accepting larger dies, poorer yields, and longer manufacturing times. They may also lean on advanced packaging to extend the life of DUV technology. Douglas Fuller from Copenhagen Business School expects these methods to allow firms to handle the latest DRAM generations by the end of the decade. However, the limitations are clear. Micron eventually adopted EUV for its 1-gamma DRAM to achieve a 30% increase in bit density. Mack argued that it would be difficult to believe a 3nm or 2nm logic node could be economically viable without EUV. While China aims for 70% AI chip self-sufficiency by 2030, the reliance on DUV ensures that costs and efficiency gaps will persist.

The situation leaves open questions about the long-term sustainability of the DUV-only approach. While companies like CXMT can grow capacity, the underlying physics of multiple patterning imposes a hard ceiling on performance. The industry now faces a landscape where Chinese firms can compete in specific segments like memory by absorbing higher costs, but the gap in logic chip manufacturing remains wide. As the decade progresses, the interplay between EUV availability and DUV innovation will continue to define the global semiconductor supply chain.